1. Field of the Invention
The present disclosure relates to semiconductor package, and more particularly, to a leadframe, a package assembly and methods for manufacturing the same.
2. Description of the Related Art
With an increasing demand for miniaturization, light weight and multiple functions of electronic devices, a semiconductor package is developed towards a high packaging density so that a package size can be reduced. A package assembly using a leadframe and encapsulating a plurality of integrate circuit chips has attracted attention. In such package assembly, arrangement of the integrated circuit chips and their connections have significant effects on the package size and properties of the electronic devices.
FIG. 1 is a perspective view showing a conventional multi-chip package assembly 100. In package assembly 100, two integrated circuit chips 120 and 130 are arranged side by side on a leadframe 110. The leadframe 110 includes a plurality of finger-like leads 111. Each lead 111 has an upper surface with an interconnect area thereon. Conductive bumps 121 are provided at a lower surface of a first integrated circuit chip 120, with their ends soldered to the interconnect areas of some of the leads 111 by solders 122. Contact pads of a second integrated circuit chip 130, at a lower surface, are soldered to the interconnect areas of other ones of the leads 111 by solders 131. The leadframe 110 and the integrated circuit chips 120 and 130 are encapsulated by an encapsulant 160. At least some portions of the leads 111 in the leadframe 110 are exposed from the encapsulant 160, for electric connection with external circuits, such as a PCB (i.e. printed circuit board).
FIGS. 2a to 2d are cross sectional views illustrating various steps of a method for manufacturing the conventional package assembly 100. The first integrated circuit chip 120 is placed on a leadframe 110, with solder balls 122 contacting the leadframe 110, as shown in FIG. 2a. A reflow process is performed so that the solder balls 122 are melted to form solders 122, as shown in FIG. 2b. Thus, the first integrated circuit chip 120 is secured on some of the leads in the leadframe 110 by the solders 122. A second integrated circuit 130 is then placed on the leadframe 110. Another reflow process is performed so that the second integrated circuit chip 130 is secured on other ones of the leads in the leadframe 110 by the solders 131, as shown in FIG. 2c. The leadframe 110 and the integrated circuit chips 120 and 130 are then encapsulated by an encapsulant 160 (for example, epoxy resin) to form a package assembly 100, as shown in FIG. 2d. 
In such conventional package assembly, the integrated circuit chips 120 and 130 are arranged side by side on the leadframe 110. The integrated circuit chips 120 and 130 may be electrically coupled to each other by sharing some leads in the leadframe 110. Alternatively, the integrated circuit chips 120 and 130 may be electrically coupled to each other by attaching bonding wires.
Nevertheless, the arrangement of the integrated circuit chips 120 and 130 side by side is disadvantageous in terms of the packaging density, because the resultant package assembly 100 occupies an area larger than a sum of footprints of the integrated circuit chips 120 and 130. Moreover, the integrated circuit chips 120 and 130 are subjected to reflow for two times before encapsulation by the encapsulant 160. The second reflow process may cause an undesirable reflow of the solders 122 of the first integrated circuit chip 120, which has been subjected to reflow already. Consequently, the interconnect may be damaged.
A stacked package assembly is also proposed, in which a plurality of integrated circuit chips are stacked on a leadframe. An integrated circuit chip in the lowermost level is secured on a leadframe by soldering. Integrated circuit chips in an upper level may be secured by adhesion on top surfaces of integrated circuit chips in a lower level. The integrated circuit chips in the upper level may be electrically coupled to the leadframe by bonding wires. Although the stacked package assembly can reduces its footprints, the bonding wires are used in the package assembly, which results in a complex bonding process and an increased manufacture cost. The electronic devices may suffer from poor electrical contacts of the bonding wires, or even failure.
Thus, it is desirable that the packaging density of the package assembly is increased while its reliability is improved.